The present invention relates to the conversion of analog signals to digital signals and particularly to a pipelined analog-to-digital converter. It relates also to an interstage amplifier for use in such a converter.
Much attention has been devoted in the art to the design of an analog-to-digital converter which can produce conversion at high sampling rates, with a minimum of delay through the converter, with reasonable accuracy and with low cost and/or minimum occupation of area if the converter is to be incorporated as an integrated circuit or part thereof. The most rapid known form of conversion is byway of a `flash` converter, in which the input analog signal is applied to a multiplicity of comparators arranged to provide a digital output in minimum time, i.e. one clock cycle. However, the number of comparators required in a flash converter increases exponentially with the accuracy required, with attendant increases in cost and area occupied by the converter. It is also known to provide a two stage or sub-ranging converters. However, even these converters suffer from excessive growth of the area, power consumption and input capacitance with the number of bits resolved and there are difficulties inherent in cancelling offsets and mismatches. Although both flash and subranging converters are adequate for some applications, they are generally unsatisfactory for applications that require a resolution greater than ten bits.
A form of converter which shows at least theoretically more benefits in terms of area, power consumption, input capacitance and cost is a pipelined analog to digital converter. In a typical form of such a converter, there is at each stage a resolution of only a small number of bits (typically only one bit) and a residue obtained by comparing a reference signal with a multiplied version of the input analog signal is passed to the next stage of the converter. In a simple version, although there are more complex versions to which reference will be made later, an input signal may be multiplied by two and compared with a reference signal. If the multiplied input signal to the stage is greater than the reference signal, the bit output for that stage is unity (1) whereas if it is less than the reference signal the bit output for that stage is zero (0). A residue may be formed by, depending on the comparison, either the multiplied signal itself or the difference between the multiplied signal and the reference signal. This residue is again multiplied by two and compared with the reference signal to provide the next least significant bit and so on.
A pipelined analog-to-digital converter of this general type requires an interstage amplifier which preferably is based on an operational (i.e. very high gain) amplifier which employs switched capacitors. Such an amplifier and, for example, a single comparator and associated FET transistor switches constitute the comparatively small number of components needed for each stage of the converter. Accordingly, a pipelined converter is at least theoretically more convenient for high resolution applications than flash converters or subranging converters.
However, pipelined converters suffer from several imperfections such as offset, gain error and a variety of non linearities which require to be eliminated or at least compensated before the converter is appropriate for use at high sampling rates and with high resolution.